I have completed a VHDL 16-bit parity generator and I would like to know if I have programmed it correctly. I have compiled it 10 times and worked out any bugs that it found. I was finally able to compile it successfully. My problem is that I am trying to run a timing simulation to make sure it will work correctly but I am not sure what I should be looking for. The basic operation is to XOR the A and B inputs to perform an iterative process with an output of '1' as odd and an output of '0' as even. My code is written such that a basic XOR block is then added as a component of the complete parity generator.

I would like a second opinion to make sure I have written it correctly and if it will do what it is designed to do. I thank you all in advance and look forward to any input, good or bad. Microsoft word 2007 thaiware maintenance. Basic XOR gate block VHDL Code library ieee; use ieee.std_logic_1164.all; entity xor_gate is port( a: in std_logic; b: in std_logic; pari: in std_logic; paro: out std_logic); end xor_gate; architecture behavior of xor_gate is begin paro. Trudoemkostj rabot lada largus 1. As mentioned in the comments the or part of your 'xor_gate' prevents it from actually working as an xor gate to calculate bit parity.

The VHDL source code for, checker, control state machine, and status bit Parity generator Command/data mux Cypress Semiconductor Original. 647.54 Kb vhdl code program for 4-bit magnitude comparatorAbstract: vhdl code for 4 bit ripple COUNTER 8-bit magnitude comparator 16- bit even/ odd parity generator/ checker, Quad 2-inupt EXCLUSIVE NOR.

Instead your paro signal will be '0' when a=b and '1' when a/=b (the 16 bit vectors, not the bits within xor_gate). If that was your intended functionality, then paro.